Mentor Forum 2019 Seoul ??? PDF ????

AGENDA

??? ?? ???? ??????, ?? ??? ?? ?? ? ??? ???? ???? ??? ???? ?? ??? ?? ???? ??? ???. ???(assertion) ?? ???? ???? ??? ?? ????? ?? ?? ???? ??? ????? ??? ?? ?? ?? ??? ? ??? ?? ??? ??? ??? ?? ??(?? ????? ??? ???? ??? ??)? ???? ???? ???? ??. ? ????????? ???? ?? ?? ??? SoC ?? ????? ??? ?? ? ?? ??? ????. ?? ???? ????? ?? ??? ?? ??? ???? ?? ??????? ????.

As we have shown in prior Mentor Forums, one of the biggest developments in the verification world in has been the industry-wide adoption of automated, formal-based ?apps?. Requiring no prior knowledge of assertion-based verification or formal methods, formal apps combine automated, exhaustive formal analysis under-the-hood with well-documented methodologies focusing on specific, high-value verification challenges that are poorly served by other technologies. In this presentation we will show examples of where formal apps can accelerate specific SoC-scale verification tasks ? both by reducing the required setup time and wall clock run time vs. traditional approaches.

?? ??? ?????? ?? ???? ?????, ?? ??? ???? ?????? ???? ? ???? ???? ???? ???? ?? ???? ????. ??? Solido Design Automation?? ?????? ? ??? ???? ???? ??? ???? ?? Variation Designer? ML Characterization Suite? ??? ???? ?? ? ???? ?????? ?? ???? ???. ? ????? Solido Variation Designer? ?? ??? ????, Solido?? ??? High-Sigma Verifier? ????. ? ??? ?? ????? ???? ??? ??? ??? ??? ?? ? ?? ???? ??? ?????. ?? ML Characterization Suite? ???? ???? ????? ?? ??? ??? ??? ??? ???? ?? ????. ????? ???? ??? ????? 2? ?? ????, .LIBs? ???? ?? ??? ? ??? ??? ?? ? ?? ?? ????.

At lower nodes, increasing process variability requires innovative verification solution to ensure design quality robustness and meet the reduced time to market needs. With the acquisition of Solido Design Automation, Mentor became the leading provider of variation-aware design and characterization software with Solido?s Variation Designer and ML Characterization Suite powered by proprietary machine learning technologies. In this session we will cover the latest capabilities in Solido Variation Designer and introduce Solido?s new High-Sigma Verifier, a next-generation tool with algorithmic breakthroughs that make high-sigma verification faster and easier than ever before. We will also explore how library teams and digital teams benefit from ML Characterization Suite?s machine learning methodology, enabling 2X+ runtime speedup for library characterization, and comprehensive validation of .LIBs within hours instead of weeks.

? ????? ??? ?? ??? Symphony Mixed-Signal Platform? ?? ??? ????. Symphony? ???? ?? ??? ?? ??? ?? ???? ??????, ?? ??, ??? ? ??? ?? ????? ?? ???? ????/???(A/D) ????? ??? ?? ???? ????. Symphony? ??? ????? ??? Analog FastSPICE(AFS) ?? ?????? ??? ??? ??? ??, ???? ????. AFS? ?? 5nm FinFET ??? ???? ???? ??? ????, ????(nm) SPICE ???? 20M? SPICE ???? ??? ????. AFS? ???? ?? ????, RF, ????, ??? ? ??? ??? ??? ?? ???? ???? ??? ????. AFS ??? Symphony? ???? ?? ??? ???? ??????? ?? 2?? ?? ??? ?? ?? ??? ?? ?? ? ?? ??? ??? ????.

In this session we provide an in-depth overview of Mentor?s recently launched Symphony Mixed-Signal Platform. Symphony is the industry?s fastest and most configurable mixed-signal solution to accurately verify design functionality, connectivity, and performance across analog/digital (A/D) interfaces at all levels of the design hierarchy. Symphony?s modular architecture leverages Mentor?s Analog FastSPICE (AFS) circuit simulator for performance, capacity and accuracy. AFS is foundry certified up to 5nm FinFET-based processes, provides nanometer (nm) SPICE accuracy and capacity of 20M SPICE elements. AFS provides high performance circuit verification for nanometer analog, RF, mixed-signal, memory, and custom digital circuits. Symphony powered by AFS provides customers with an average performance improvement of 2x over previous generation mixed-signal simulators along with best-in-class use model and advanced debug capabilities.

?? ????? ??? ??? ? ?? ????? ????? ??, ? ?? ? ??? ???? ?? ???? ?? ????? ??? ?? ???. ?? ?? ?? ??? ?????, ?? ???, FDSOI, FinFET ???? ? 3DIC? ?? ??? ?? ??? ??? ??? ??? ??? ? ?? ?????? ??. Calibre xACT? 3D ???? ??? ??? ??, ????? ? ????? ??? ?? ?? ??? ?? ?????? ??? ??? ???? ??? ???? ?????? ????? ??? ???? ??? ?????? ??? ?? ???.

Circuit designers want to achieve first time silicon success and one of the objectives is to get circuit simulation results that closely match silicon. This is the goal at any process node but is made more difficult when you consider new design requirements and process effects such as high frequency, FDSOI, FinFET devices, and 3DIC. Calibre xACT leverages 3D parasitic extraction technology to accurately model resistance, capacitance and inductance effects on the interconnect across multiple process corners to give designers confidence that their simulation results will match silicon performance.

"H/W????? Manual? ???? PCB Checklist??(SI/PI/EMI ?)? HyperlynxDRC? Custom Rule? Web??? ???? ?? ???? ?? ???? ???. PCB Design File(ODB++)? Web Server? ??? ??, ????? ??? ? Custom Rule? ???? pass/fail ??? ???. ?? ?? ??? ???? Output Format? ??? ???? ????, ??? Web? ??? DB? ????, ??? ?? ??? ??? ???

Samsung has completed a system that enables H / W developers to automatically verify the PCB Checklist items (SI / PI / EMI, etc.) that are being validated by manual using HyperlynxDRC's custom rule and web technology. Once the PCB Design File (ODB ++) is uploaded to the Web Server, it is transferred to the analysis server and verified whether it is pass / fail using Custom Rule. The detailed verification result is automatically created according to the defined output format and saved in the DB connected to the web upon completion. And the result is forwarded to the internal mail simultaneously.

? ????? ??? ?? ??? ??? ??? ?? ? ?? ???? ??? ?? ?????. HyperLynx ?????? ?? update ??? ?? Xpedition AMS?? automation? ??? parasitic extraction ??? ?? ??? ??? Xpedition Enterprise Flow??? 2.5 ? 2.6 Release?? ??? Sketch routing ? RF? ?? ??? ??? ?? complex via control?? ?? ?? ?????.

In this session, we will discuss new features including recent product improvements as well as future roadmap and vision. Regarding HyperLynx product family, we will describe, along with other updates, the parasitic extraction function that uses automation in Xpedition AMS. And, for Xpedition Enterprise Flow, we will introduce improved Sketch routing and RF functionalities for Releases 2.5 and 2.6 as well as complex via control function for high-speed signal design and others.

??? ??? ? ?? ???? ?? ?? ??, ???????(System-in-Package)? ? ??? ???? ??. ???? ????, ???, ??? IC? ?? ?? ??, ?????, ????, MeMs ? ??? ??? ??? ????? ???? ??. ? ?? ????? ?? ???? ??? ?? ? ??. ??? 5G??? ?? ?? ??, ???? ? ?? ???? ??? ????? ?? ???? ????? ???. ?? ?? ???? ?? ?? ??? ??? ??? ??. ? ??? ???? ??? ??? ? ?? ???. 5G? ???? ???? ??? ????? ????.

As Moore's Law no longer holds, System-in-Package is taking hold. A system comprises many components including analog, digital, power ICs, as well as passives, transistors, diodes, MeMs and sensors. All of these components can be assembled into a single package. The problem is that 5G is driving the need for very high density advanced packaging with 10's of thousands of pads, interposers and die stacking. Current popular design tools are breaking - they simply can't handle the capacity of design. A different approach is needed to make 5G a reality.

????? ?? ??? ???? ??? ?? ???? ????. ? ????? ??? ??? ?? ???? PCB ??? ?? ???? ECAD-MCAD?? ????? ?????. ??? ??? ?? ????? ??? ??? 3D???? ???? ?? ???? ? ?? Xpedition ??? 3D ??? ????? ?????.

ECAD engineers are struggling to improve product development efficiency. This session introduces ECAD-MCAD collaboration process between PCB design and mechanical design as an answer to this challenge. This session will discuss the synergy effect of business through real-time collaboration and the usefulness of 3D design, and introduces the case of 3D design application of Xpedition customer around the world.

??? Austemper Design Systems?? ??? ??? ??? ?? ? ???? ?? ??? ??? ??? Mentor Safe IC? ?? ???? ?? ?? ???? ???? IC ?? ?? ??? ??? ??? ??? ???. ? ????? Mentor Safety IC? ??? ????, ?? ?? ??? ??? ???? ?? ? ???? ??? ???? ??? ????.

Combining Mentor?s acquisition of Austemper Design Systems with existing Mentor and Siemens technologies, Mentor Safe IC provides the most comprehensive functional safety solution to bring increased automation for the entire IC functional safety flow. This session will provide an overview of Mentor Safety IC and how it can help increase your efficiency, shorten development cycles and reduce risk.

???(??) ??? ? ???? ???? ??? ? ??? ?? ?? ??(Plan Driven) ? ?? ??(Requirements Driven) ???? ??? ?? ? ????. ??? ??? ???? ?? ?? ?? ??? ????? ??? ??? ???? ??? ?? ????? ????. ?? ??? ???? ??? ??? ? ???? ?? ????? ?? ??? ???? ????. ??? ??? ?? ??? ?? ????? ?? ???? ??? ? ??. ?? ?? ?? ????? ??? ??? ????/????? ???? ??????? ???? ??? ??? ???? ?? ??? ?? ? ??. ??? ???? ??? ???? ISO26262 ?? DO-254? ?? ?? ?? ??? ????. ?? ??? VHDL/Verilog ?? ?? ???? ??? ?? ??? ?? ? ??. ???? ??, ? ???? ???? ???? ??? ??? ??. ?? ?? ??? ??? ???? ??? ?? ?? ?? ?? ????? ?? ?? ?????? ?? ?? ???? ???? ?????. ?????, ???? ???? ??? ??? ??? ??? ??? ? ??? ??? ?? ???(agnostic)??? ??. ? ????? ???? ??? ?? ?? ??? ??? ???, ?? ?? ? ?? ??? ?? ???? ?? ??? ?? ???? ??? ? ??? ?? ?? ????.

Being able to author a test (verification) plan in a collaborative team environment is an important aspect of both Plan Driven and Requirements Driven methodologies. Once the test plan is defined, the common verification process is driven by ensuring that all the design features are being successfully tested. This is achieved by linking the tests and coverage model references defined within a test plan to the results of verification. The connection from the test plan to the design specification can be loosely bridged by the Verification Engineer. Alternatively, a requirements management system can hierarchically decompose system requirements through to hardware/software requirements, and onto test plans with verification results. This detailed level of traceability is a requirement of functional safety standards such as ISO26262 or DO-254. There may also be demands for traceability and audit between the design requirements and the VHDL/Verilog implementation. Ideally a smooth path should exist between the two methodologies, enabling a project to migrate from Plan Driven to Requirements Driven when it becomes necessary to fulfil the demands of safety critical standards. As well, an ideal solution should be agnostic to allow different data formats and tools to be supported. This session will highlight that Siemens and Mentor are in a great position and can offer a single solution to address both Plan Driven and Requirements Driven verification methodologies.

??, ??? ? ?? ??? ???? ??? ???? ?? ????? ????? ??. ?? ??? ????. ??? ??????? ??? ???? ?????? ??? ???? ?? ????? ??? ????. ??? ??? ??? ????? ???? ???? ???? ???? ? ??. ???? ?? ??? ??? ? ?? ??? ??? ??? ??, ? ??? ??? ????? ???. ? ???????? ??? PAVE360? ??, ???? ? ????? ????? ??? ???? ???? ??? ??? ??? ???? ??????.

Sensing, Computing and Actuating components need to be included in any comprehensive verification process of autonomous vehicles. This presents a significant challenge, since it isn?t practical to do physical prototyping and use trial-and-error approach to find issues. And we can?t test safety and security thoroughly in a real, physical vehicle. The only way we can do an extensive verification job is to virtualize the entire system ? environment and vehicle. This presentation will describe PAVE360, an innovative approach based on new methodology that combines verification and modeling of sensors, electronics and mechatronics components.

????? SoC? ??/??? ? ?? ???? ???? ISO 26262 ?? ??? ??? ????? ??. ISO 26262? ?? ?? ??? ??(ASIL: Automotive Safety Integrity Level)? ??? ????? ????. ??? ??? ???? ???? ?? ???? ? ??? ??? ?? ?? ????? ????? ???. Tessent MissionMode ????? Tessent LBIST ? MBIST ??? ??? ? ??? ??? ????. ??? ? ?? BIST? ?? ??? ??? ????? ??? ? ????? ???? ??????? ??? ? ??. ? ??? ????? ??? ???? ???? ??? ????, ?? ?? ??? ??? ?? ??? ?????. Tessent TK/LBIST ???? ?? ??? ??? ??? ?? ???? ???? ???? ? ??. Tessent MissionMode ???? ??? Tessent MBIST? ?? ??? ???? ???????? ??? ? ??. ?? Tessent MBIST? ?? ?? ??? ??? ??? ????? ?????, ?? ???? ????. Tessent DFT ???(Tessent MissionMode/MBIST/LBIST)? ??? ? ???? ??? ?? ??? ??? ??? ? ?? ??? ????. Tessent DFT ??? ???? ?? ?? ??? ??? ?? ???? ???? ????? ??? ? ??. ?? ????? ? ????? ??? ???? ??? ??? ?? ???? ????.?

"Automotive SoCs should consider quality/reliability and functional safety and meet ISO 26262 functional safety requirements. ISO 26262 defines Automotive Safety Integrity Levels (ASILs) to designate risk potential. One approach to ensuring the reliability of a vehicle?s electronics is to perform periodic testing during functional operation. The Tessent MissionMode architecture provides in-system test method based on Tessent LBIST and MBIST. In-system logic BIST, which is scan-based structural testing, can be used for safety and mission critical applications. This test solution involves the on-chip generation of random patterns that are applied to scan chains to detect logic defects. Tessent TK/LBIST flow enables the maximum optimization of defect coverage considering test time. The Tessent MBIST based on Tessent MissionMode architecture can detect a latent fault and soft-repair it. Also, Tessent MBIST provides very high quality memory test algorithms which are verified in field. Tessent DFT platform (Tessent MissionMode/MBIST/LBIST) provide an easy method to implement in-system testing and a powerful verification environment. Tessent DFT platform flow is available in the Samsung Foundry reference flow based on the open core design. Samsung Foundry provides a complete turnkey solution from chip design to package test."

HLS? ??? ???? ??? ?? ?? Catapult? ???? HLS IP? C++ ?? SystemC? ??? ??? ?????? ???? ???? ? ? ????. ??? ??? ????(QofR)? ???? ? ??? ??? ?????. ? ????? ????? ???? Math ? DSP ??? ???? ?? IP?, ??? ??? ?? 2D ????? ??? ?? ??? ?? ? ?? CNN(tinyYOLO) ??? ??? ?? ?? ???? ???? ?? ????.

To accelerate and ease the adoption of HLS, Catapult provides both building block HLS IP and various application reference designs written in C++ or SystemC that are designed to help deliver optimal QofR. This session will describe the available IP including the Math and DSP blocks available as open-source and the several reference designs, including 2-D convolution for image enhancements and two CNN (tinyYOLO) implementations for real-time object classification.

???? ?? ?? ??? ?? ?? ?? ?? ??? RTL(????)??? RTL freeze(?? ??) ??? ????? ???? RTL IP? ??????? ??? ? ??? ?? ??? ??? ???? ? ?? ??? ?? ??? ??? ?????. PowerPro? ??? Veloce Emulation Platform?? ???? ??? ???? ????. ?? ?? ??? ???? ?? ?? ?????(time to power)? ????, ?? ?? ? ASIC/SoC? ?? ??? ?? ????(????? ?????? ? ? ????)? ??? ?? ??? ?????. ? ????? PowerPro? ?? ??? ? ??? ??? ???? ?? ?????? ?? ??? ????? ???? ??? ????.

Design teams today need a true metrics-driven low power methodology that can measure their RTL IP ?quality for power? at very early stage RTL(vectorless) through RTL freeze (power vectors) and be easily integrated into your regression environment. PowerPro offers a tightly integrated flow with Mentor?s Veloce Emulation Platform that delivers the fastest time to power for the largest designs; enabling power analysis with realistic scenarios (executing both hardware and software) for the full ASIC/SoC. this session will show how PowerPro's advanced debugging and optimization and how it can deployed for effective user of both emulation and compute resources.

HYCON ???? ?? ??? ??? SoC? ???? ?? SW/HW ???? ? ????? ??? ???? ??? ??? SW/HW IP? ??? ??? AP? ? ?? ??? ???? ? ???? ???. ??? ???? QEMU[1] ?????? HW ?????? ?? ?????? ???? ??. ????? ???? ??? ?? ???? CPU, eMMC, CLCD ? ????? ?? IP? ??? QEMU ????? ?? ???? SW? ?? ??? ?????. ??? ?? IP? ??? ?????? HW ????? ?? ???? RTL(Register Transfer Level) ???? ??? SW ??? ??? ????. ?? IP? ??? ?? IP? ?? ??? QEMU ????? ?????. ?? ??? ? ?? ??? ??? ???? ???? ????. ?????? ????? ????? ???? ??? ??? ???? ?? 10? ?? ??? ? ???, SW ????? IP? ???? ??? ??? ?? ??? ????? ?? RTL? ??? ????? ?? ? ??? ? ??? ? ? ??.

The main purpose of HYCON methodology is to enable both SW/HW co-design and co-verification prior to building matured SoC, thus contributing to the reduction of total development period for mobile APs by securing early-verified SW/HW IP. The proposed methodology adopts co-emulation of QEMU[1] simulation and HW emulation. Most of the IPs such as CPU, eMMC, CLCD and peripherals, which are used frequently for Android platform boot-up, are allocated to the QEMU simulation side, which maximizes run-time performance of SW. The only target IPs and memory subsystem are allocated to HW emulator side to help start SW development with RTL (Register Transfer Level) design. Except the target IP, all of IPs are the QEMU library models which are already verified. It is fast to bring-up the Platform including compilation and running time. Application results show that booting an Android platform can be completed within 10 minutes on the proposed methodology, and show that SW driver and IP?s firmware are successfully developed and validated with RTL before the silicon based development board is ready.

HYCON ???? ?? ??? ??? SoC? ???? ?? SW/HW ???? ? ????? ??? ???? ??? ??? SW/HW IP? ??? ??? AP? ? ?? ??? ???? ? ???? ???. ??? ???? QEMU[1] ?????? HW ?????? ?? ?????? ???? ??. ????? ???? ??? ?? ???? CPU, eMMC, CLCD ? ????? ?? IP? ??? QEMU ????? ?? ???? SW? ?? ??? ?????. ??? ?? IP? ??? ?????? HW ????? ?? ???? RTL(Register Transfer Level) ???? ??? SW ??? ??? ????. ?? IP? ??? ?? IP? ?? ??? QEMU ????? ?????. ?? ??? ? ?? ??? ??? ???? ???? ????. ?????? ????? ????? ???? ??? ??? ???? ?? 10? ?? ??? ? ???, SW ????? IP? ???? ??? ??? ?? ??? ????? ?? RTL? ??? ????? ?? ? ??? ? ??? ? ? ??.

The main purpose of HYCON methodology is to enable both SW/HW co-design and co-verification prior to building matured SoC, thus contributing to the reduction of total development period for mobile APs by securing early-verified SW/HW IP. The proposed methodology adopts co-emulation of QEMU[1] simulation and HW emulation. Most of the IPs such as CPU, eMMC, CLCD and peripherals, which are used frequently for Android platform boot-up, are allocated to the QEMU simulation side, which maximizes run-time performance of SW. The only target IPs and memory subsystem are allocated to HW emulator side to help start SW development with RTL (Register Transfer Level) design. Except the target IP, all of IPs are the QEMU library models which are already verified. It is fast to bring-up the Platform including compilation and running time. Application results show that booting an Android platform can be completed within 10 minutes on the proposed methodology, and show that SW driver and IP?s firmware are successfully developed and validated with RTL before the silicon based development board is ready.

???? ??? Portable Test and Stimulus ??(PSS)? ??? ??? ????? ?? ???? ??? ???? ??? ????, ???? ??? ?? ???? ????, ??? ???? ??? ???? ??? ??? ? ??. ??? ??? ??? ??? ??? ??? ?? ??? ??? ? ?? ??? ??? SystemVerilog UVM ????? ??? ??? ? ??? ??? ???? ?? PSS? ??? ???? UVM ?????? ???? ??? ?????, ?? ?? ??? ??! SystemVerilog? ?? inFact? PSS ?? ??? ?? ????? ????? ???? ?? ?? ??? ??? ??? ??? ??? ?? ??? ??? ? ??. inFact PSS Apps? ??? SystemVerilog ??? ? ????? ?? ???? ??? ?????? ??? ??? ? ??? ?? ???? ????. inFact PSS Apps? ??? ?? ????(correct-by-construction)? SystemVerilog ????? ???, ???? ?? ?????? ??, ??? ???? ??? ? ?? ??? ?? ???? ?????? ??? ?? ? ?? ? ?? ?? ???? ???.

Modeling scenarios with the new Portable Test and Stimulus language (PSS) enables users to focus on the high-level requirements of what they need to test, and use automation to create specific valid tests and make those tests portable across a range of verification environments. Wouldn?t it be great if we could bring this same ability to focus on what we want to test instead of how to our existing SystemVerilog UVM testbench environments? We most certainly can by adding PSS-created tests to our UVM testbenches, but there?s an even easier way! inFact?s PSS Apps for SystemVerilog leverage the same core algorithms that enable PSS users to focus on what they want to test, not how. But, the inFact PSS Apps read in existing SystemVerilog classes and covergroups, allowing you to make the most of your existing testbench, while also increasing your verification productivity. Come see how the inFact PSS Apps can help you create correct-by-construction SystemVerilog covergroups, analyze your constraints pre-simulation, and generate efficient stimulus for coverage closure and bug hunting.

??? ?? ?????? ???????? ?? ??? ?? ?? ? ??. ??? ???? ???? ???? DRC? ???? ?? ?? ?? ??? ?? ????, ???? ??? ?? ??? ??? ?? ?? ?? ?? ??. ??? ??? ???? ?? Calibre DRC ???? ??? ??? ????? ??? ??? ?? ?? ?? ??? ?? ??? ???? ??. ? ???? ???? ??? ??? ??? ????? ?? ?? ???? ?? ?? ?? ????? ??? ??. ?? P&R ????? ???? DRC ??? ?? ??? ?? DRC? ??? ??? ??? ???? ???, ?? ????? ??? ???? ??? ??? ??. ? ????? ??? Calibre RealTime Digital? ??? ???? DRC ???? ????? ??? 60??? ?????? ???? ???, ??? ? ??? ????? ????? ??? ????.

Often initial design iterations may have floor planning or placement issues. Running full blown sign-off DRC in such conditions will typically result in very long runtimes with millions of mostly meaningless results. To combat this challenge, the Calibre DRC team is introducing several new enhancements to simplify and speed such runs. In this session users will learn the details of these new features and best practices of when to use them. Moreover, P&R engineers spend a significant amount of time to fix last mile DRCs during sign-off DRC closure, which directly impacts their tapeout schedule. This session also presents how a customer uses Calibre RealTime Digital to reduce the turn-around time for sign-off DRC closure by 60% while optimizing their designs for timing, reliability and manufacturability constraints.

?? ??? ???? ?? ?? ?? ?? ???? ? ??? ?? ???? ???? ???? DRC? ???? ?? ?? ?? ????? ????? ??. ??? ??? ??? ?? ?? ???? ???? ??? Calibre?? ?? ??? ???? ??? ???? ???? ?? ???? ??? ???. ? ???? ???? ??? ??? 5nm ??? ?? ??? ??? ???? ?? ???? ?? ??? ?? ?? ? ???, Calibre? ??? ??? ??? ??? ?? ???? ???? ??? ?? ??? ??? ??. ???? Calibre? ???? ???? ???? ?? ?? ???, ???? ???? ??? ??? ??? ??? ???? ????.

As design sizes grow, number of routing layers increase, and rule deck counts and complexity explodes, managing sign-off DRC in reasonable runtimes becomes a challenge. To help address these concerns, the use of cloud computing to enable Calibre?s unparalleled massive scalability becomes attractive. In this session, users will learn some of the new design challenges as Moore?s Law marches to 5nm and below, and best practices with Calibre to address them in the most efficient way possible, including running Calibre in a cloud configuration as well as new features targeted at reducing the cloud hardware costs.

Calibre LVS? ??? ???? ????? ??? ???? ?????, ??? ???? PEX ?? ?? ??? ?? ?? ????? ??? ?? ??? ???? ???? ?? ??? ?????? ?? ?? ???? ???? ? ????? ????? ?? ?? ??? ??? ?????? ???? ??. ??? ?? ??? ?? ???? ??? ?? Calibre LVS? ??? ?? ??? ???? ???? ?? ???? ???? ??? ?? ???? ??.

New methods to dramatically improve turn around time, and support PEX tools in advanced as well as established nodes, with new techniques to address more complex device parameters extraction that takes Calibre LVS from a circuit verification tool to a crucial high performance interface to parasitic extraction and downstream simulation tools. With the new design requirements and increasing process necessities, Calibre LVS is continuing to be the industry standard platform to achieve reliable and accurate silicon.

Calibre PERC? ???? ???? ??? ??? ???? ??? ?? ?? ??? ??? ??? ????? ?? ?? ?????? ?? ?? ?????. ?? IP, ?? ? ?? ????? ??? ?? ??/??/???? ?? ??? ????. ??? ?? ? ???(ESD/LUP) ??? ?? ???? ??? ???? ? ??? ??, ?? ?? DRC, ??? ???(EOS) ? ???? ???? ?? ??? ?? ?? ???? ????.

Calibre PERC is a verification solution for circuit designers looking to validate their design is robust against common causes of electrical failure. Calibre PERC is a high-performance engine that has the performance/capacity/accuracy for verification at the IP, block, and full-chip level. Sign-off level foundry rule decks are available for Electrostatic Discharge and Latch-Up (ESD/LUP) verification as well as other solutions for Voltage-Aware DRC, Electrical OverStress (EOS), and Analog Constraint Checks.